Yield-Optimal Cell Layout Synthesis for CMOS Logic Cells

The recent improvement of VLSI process technologies enables us to integrate a large number of transistors on one chip, and significantly improves the circuit performance. On the other hand, the methodology of VLSI design becomes more and more complex and some new problems, such as Design For Manufacturability (DFM) have arisen. Due to the very high costs associated with the manufacturability of sub-micron integrated circuits, even a modest yield improvement can be extremely significant. In order to achieve the high yield, a standard-cell layout synthesis considering the DFM is required since standard-cells are the most basic elements of the cell-based design methodology as described in Chapter 1. This chapter describes a comprehensive CMOS logic cell layout synthesis technique for yield optimization by minimizing the sensitivity to wiring faults due to spot defects. Spot defect is one of the main sources of electrical failure in VLSI integrated circuits. We modeled the sensitivity to wiring faults on intra-cell routings with consideration to the spot defects size distribution and the end effect of critical areas. Critical area is defined as the area in which the center of a spot defect must fall to cause a fault. We comprehensively generate the minimumwidth layouts of CMOS logic cells and the exact optimal layouts are selected from all the possible minimum-width layouts by using our model of the sensitivity to wiring faults as a cost metric. Although the critical area used for the sensitivity calculation is extracted from the original layout patterns, the feasibility of the proposed sensitivity model to the practical lithography system is discussed. Moreover, the adequacy of the proposed sensitivity to the other cost metrics such as the cell delay and the total intra-cell wire length is demonstrated. The impact of the sensitivity reduction on the yield is also discussed in this chapter.